Application-specific integrated circuits (ASICs) and other types of complex electronic circuits are often designed using Register Transfer Level (RTL) techniques. In an RTL-based design process, the design is initially expressed in a high level Hardware Description Language (HDL) such as VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL), which is a standard of the Institute of Electrical and Electronics Engineers (IEEE). At the HDL level, the "behavior" of the design (e.g., inputs, outputs, functionality, etc.) is entered into a computer and then the design, as expressed in the HDL, is converted to a gate-level description (a "netlist") using a process referred to as synthesis. The synthesis process optimizes the gate-level description within the area and timing constraints of the particular design in a well known manner.
ASICs and other complex circuits may also make use of Design for Test (DFT) techniques which modify the design to ensure that the final gate-level design is testable for internal faults such as "stuck-at-one" or "stuck-at-zero" conditions on signal lines. A gate-level design is generally considered testable if it is possible to obtain a sufficiently high fault coverage by using test vectors generated by an automatic test pattern generator program or by on-chip logic configured to provide a function referred to as Built-In Self Test (BIST). BIST eliminates the need for off-chip test pattern generation and allows at-speed testing by embedding test pattern generation and signature computation hardware within the design.
Scan based BIST is widely used in gate level circuits, and utilizes scan chains to apply random vectors and observe signal values within the random logic at every flip-flop in a well known manner. Random pattern resistant faults are addressed by inserting carefully chosen test points after the circuit has been synthesized to the gate level.
FIGS. 1A, 1B, 2A, and 2B illustrate a prior art method for insertion of test point in gate level design comprising AND gates 2 and 4. FIGS. 1A and 2A show gate level circuits which do not include test points. Two types of test points, an observation point 10 (FIG. 1B) and a control point 20 (FIG. 2B), can be inserted in the gate level design to improve BIST fault coverage. This method is described in detail in "Integration of Partial Scan and Built-in Self Test" by C. J. Lin, Y. Zorian, and S. Bhawmik (Journal of Electronic Testing, Vol. 7, 125-137, 1995), incorporated herein by reference. In FIG. 1B, the observation point 10 is connected so that the output of the node can be observed by a Multiple Input Shift Register (MISR) in a known manner. In FIG. 2B, a control point 20 is inserted into a node and is coupled to a Test Pattern Generator (TPG) which, in a known manner, allows improved controllability of the node e'. In the example shown in FIG. 2B, a generic symbol 6 illustrates an AND or an OR gate corresponding to either an AND-control point or an OR-control point.
To avoid expensive fault simulation of the complete circuit, test point insertion is typically based on probabilistic testability measures known as controllability/observability procedures (COPs). COPs are well known for estimating the controllability and observability of every signal in a gate level combinational network. Controllability (C.sub.s) is the probability that the signal s will have value 1. Observability (O.sub.s) is the probability of observing the value of the signal s at any observation point such as a primary output or a scan flip-flop. The global impact of controllability and observability can be estimated in a well-known manner by calculating the cost function U (the average number of pseudo-random patterns required to detect a fault over the complete fault set) according to Equation (1): ##EQU1##
where F is the Fault Set, .vertline.F.vertline. is the cardinality of F, and Pd.sub.i is the detection probability of fault i. For the stuck-at-fault model, Pd.sub.i can be computed from controllability (C.sub.s) and observability (O.sub.s) using Equations (2a) and (2b) as follows: EQU Pd.sub.s/0 =C.sub.s.multidot.O.sub.s, for stuck-at-0 fault at s (2a) EQU Pd.sub.s/1 =(1-C.sub.s).multidot.O.sub.s, for stuck-at-1 fault at s (2b)
1/Pd.sub.i is as the expected number of pseudo-random patterns required to detect the fault i. The effectiveness of a test point can be measured by Actual Cost Reduction (ACR), which is the amount by which U is reduced after inserting the test point. The controllability and observability values can also be used to estimate the fault coverage given a fixed number 1 of parallel pseudo-random patterns applied to the primary inputs and all flip-flops. The probability of detecting the fault i within the l patterns is given by Equation (3): EQU fc.sub.i (l)=(1-(1-Pd.sub.i).sup.l) (3)
The Fault coverage estimate is given by equation (4): ##EQU2##
Test points can be selected by computing ACR for each candidate test point and selecting the test point which maximizes ACR. Optimally, several such test points are iteratively selected until the fault coverage estimate reaches a desired value.
It has been shown in commonly assigned patent application Ser. No. 09/390,983 (entitled "Register Transfer Level (RTL) Based on Scan Insertion For Integrated Circuit Design") that the scan chain of a scan based BIST can be inserted as RTL-VHDL code within the core logic. However, nothing in the prior art teaches the insertion of test points as RTL code at the pre-synthesis level. While insertion of the scan chain as RTL code is an improvement over gate-level insertion of scan chains, it cannot achieve an optimal level of fault coverage.